Jan Reineke
Saarland University
Hardware-Software Contracts for Safe and Secure Systems
Trains, planes, and other safety- and security-critical systems that modern society relies on are controlled by computer systems, as is much of our critical infrastructure, including the power grid and cellular networks. But can we trust in the safety and security of these systems?
I argue that today's hardware-software abstractions, instruction set architectures (ISAs), are fundamentally inadequate for the development of safe or secure systems. Indeed, ISAs abstract from timing, making it impossible to develop safety-critical systems that have to satisfy real-time constraints on top of them. Neither do ISAs provide sufficient security guarantees, making it impossible to develop secure systems on top of them. As a consequence, engineers are forced to rely on brittle timing and security models that are proven wrong time and again, as evidenced e.g. by the recent Spectre attacks; putting our society at risk.
I propose to tackle this problem at its root by introducing novel hardware-software contracts that extend the guarantees provided by ISAs to capture key non-functional properties. These hardware-software contracts will formally capture the expectations on correct hardware implementations and will lay the foundation for achieving safety and security guarantees as the software level. This will enable the systematic engineering of safe and secure hardware-software systems we can trust in.
His research centers around problems at the boundary between hardware and software. In the area of real-time systems, he is particularly interested in principles for the design of timing-predictable hardware and in precise and efficient timing-analysis techniques for multi-core architectures. His recent results include the design of the first provably timing-predictable pipelined processor design (RTSS 2018) and the first exact analyses for LRU caches (CAV 2017, POPL 2019, RTSS 2019).
Another focus of his work are security vulnerabilities of hardware-software systems. Recent results include the development of automatic techniques to detect information leaks introduced by speculative execution (Spectector, S&P 2020), techniques to quantify the information leakage through cache side channels (ACM TISSEC 2015), and automatic methods to obtain highly detailed performance models for modern microarchitectures (uops.info, ASPLOS 2019).
In 2012, he was selected as an Intel Early Career Faculty Honor Program awardee. He was the PC chair of EMSOFT 2014, the International Conference on Embedded Software, a Topic co-chair at DATE 2016 and the PC chair of WCET 2017, the International Workshop on Worst-Case Execution Time Analysis. His papers have been awarded 6 outstanding paper awards and one best-paper nomination, most recently at RTSS (2018, 2019) and ECRTS (2017).
