William Jalby

The Long and Winding Road Towards Efficient High-Performance Computing

Every new hardware generation of HPC core promises major performance progress. We will present results of a detailed performance analysis of INTEL processors between 2007 and 2017 using the well-known SPEC FP 2017. We will show that performance increase cannot only rely on hardware core improvement: compiler will bring a limited part of the solution but essentially, better performance analysis and methodologies are required to drive application restructuring. We will briefly describe MAQAO/ONE VIEW toolset which has been developed according to this philosophy.
 

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Biography

William Jalby started his career first at INRIA as a Researcher, then joined the University of Illinois (CEDAR project), was appointed an Associate Professor at the University of RENNES I, then joined the University of Versailles, Versailles, France, as a Full Professor. His research interests are focusing on memory system analysis and optimization, compilers and parallelism. Most of his research has been carried out in close collaboration with hardware suppliers (Fujitsu, Bull and INTEL), tools developers (JSC, TUD, University of Oregon, CAPS Entreprise) and application developers both from research (CEA, EDF, CNRS) and Industry (ESI, MAGMAsoft, Dassault, GNS, RECOM). Since 2004, he has been the Director of a joined Lab (ITACA) between CEA DAM and UVSQ focusing on code optimization techniques. In 2010, he was appointed as CTO of the Exascale Computing Research Lab and he is leading ECR research activities
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